Design of an LC VCO for Low Phase Noise and Low Power Consumption

摘要

This paper reports design of a voltage controlled oscillator (VCO) with high oscillation frequency, low power consumption and low phase noise. The oscillator is a single stage circuit and it has a low phase noise due to reduce noise sources. The design is implemented in cadence environment with 0.18 μm UMC technology. To evaluate the performance parameters the VCO is simulated in a 0.18 μm UMC technology using specter RF simulator. In this design frequency range was varied from 2.86 GHz to 3.3 GHz. Also the phase noise of the VCO at oscillation frequency of 3.3 GHz is to 122.84 dBc/Hz @ 1 MHz offset frequency and -124.39@100 MHz offset frequency, with the power consumption of 10.71 mW and tuning range of 8.53%. In addition the present results with earlier published work has been compared and obtained improvements. Also layout is designed at supply voltage of 2V and simulated results have been verified.