Novel Approaches to Extend 193nm Immersion Technology to Advanced Device Nodes

摘要

Multiple patterning is the defacto manufacturing technology for today's advanced semiconductor devices. However, this technology is becoming limited by technical challenges including cost, resolution, overlay and defectivity. To address these challenges there is growing interest in post lithographic processes which can reduce the pattern feature size thereby effectively enabling increased resolution corresponding to low k1 imaging which is not available by single exposure schemes. In addition to increased resolution, these processes can also improve Process Window (PW), Line Width Roughness (LWR) and Critical Dimension Uniformity (CDU).