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Effective device formation for advanced technology nodes with aggressive fin-pitch scaling
Effective device formation for advanced technology nodes with aggressive fin-pitch scaling
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机译:先进的鳍节距缩放技术可有效形成先进技术节点的器件
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摘要
After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.
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