High Resolution Temperature Dependent Timing Model in Digital Standard Cell Designs

摘要

This paper introduces a new temperature dependent timing model that allows designers to deal with accurate temperature dependent delays in logic simulations. In this proposal we present the latest enhancements in the CellTherm logi-thermal simulator developed in the Department of Electron Devices, BME, Hungary. With the proposed accurate temperature dependent timing model thermal effects affecting delays in digital standard cell integrated circuits can be modeled with delay-temperature functions. In order to establish the model preliminary delay-temperature characterization is needed for the standard cells building up the circuit. We propose the extension of the industry standard Liberty format developed by Synopsys with the new model. With the new accurate model we demonstrate that present temperature-timing models do not describe temperature dependent operation sufficiently. In our presented model timing and power data can be parameterized by temperature vectors. It is also demonstrated that taking temperature dependent delays into account allows for more precise power modeling that is critical in low-power nanometer integrated systems.