A Programmable Oversampling CMOS Delta-Sigma Analog-to-Digital Converter for Low-Power Interface Electronics

摘要

In this work, 1st and 2nd order programmable oversampling delta-sigma (AS) analog-to-digital converters (ADCs) using programmable cascaded integrator comb (CIC) decimation filter are designed and fabricated in 1.5 μm and 0.5 μm n-well CMOS processes for low-power interface electronics of sensor nodes in wireless sensor networks. The designed delta-sigma ADCs can be programmed to operate at different oversampling ratios to give different output resolution bits, respectively which impact the power consumption of the sensor module in the wireless sensor networks. The major part of power consumed in the CIC decimator of the ADC is by the integrators, which operate at the highest sampling rate compared to the differentiator (approximately 725 μW at a sampling frequency of 256 kHz). Hence, an alternate design is introduced in the integrator stages by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption.