Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime

摘要

The quadratic relationship between power consumption and supply voltages encourages digital circuits to work in subthreshold regime for low- to mid-speed applications. While working under near-and sub-threshold, quasi-delay-insensitive (QDI) asynchronous circuits have the added advantages including highly robust operation and automatic adaptivity to supply voltage changes without external control/adjustment or timing analysis. This paper presents two optimization methods for QDI asynchronous circuits under subthreshold for further energy reduction: threshold voltage adjustment through body biasing to achieve minimum energy consumption at given speed requirements, and balanced gate design topology to ensure circuit's proper functioning under deep-subthreshold supply voltages. While the former enables QDI asynchronous circuits to consume optimal energy while satisfying performance requirements, the latter allows QDI asynchronous circuits to directly interface with energy harvesting and analog components, whose voltages are usually much lower than designated digital supply voltage, thereby removing the need of additional voltage translating circuits. Both methods have been demonstrated through a QDI asynchronous ALU designed using the NULL Convention Logic (NCL).