Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design

摘要

Quantum Dot Cellular Automata (QCA) is one of emerging nano technologies that serve as alternative to CMOS technology with smaller area and low power consumption. Many designs of digital circuits were proposed in QCA layout but not all are practically implementable due to random clocks in the design. There is a need for proper clocking scheme. This paper is an extension of the idea of two dimensional clocking schemes proposed earlier to multi-layered QCA circuits. The paper presents a new five input majority gate design in five layers for multi-layered circuit designs and verification of clocking scheme using 4:1 MUX and full adder designs. We use the QCA designer tool for simulations of designs.