A Sub-1 V 100 mA Wide Capacitive Load Based Flipped Voltage Follower Low-Dropout Regulator Using Transient-Assisted Embedded Driving Stage

摘要

This paper presents a new low-voltage transient-assisted Flipped Voltage Follower (FVF) based output-capacitorless low-dropout (OCL-LDO) regulator dedicated to drive wide capacitive load (C_L) range using Dual Summed Miller Frequency Compensation (DSMFC) technique. This relies on the use of low-output impedance Transient-Assisted Embedded Driving Stage (TAEDS) to enhance the slew rate at the gate of power transistor during load current (I_L) transitions whilst allowing low quiescent current (I_Q) in low supply. Validated using a UMC 65 nm CMOS technology, the simulation results have shown that the TAEDS regulator can operate for C_L ranging from 10 pF to 10 nF. Under a 0.75 V supply and a 24.6 μA quiescent current, it can deliver a maximum I_L of 100 mA with a 250 mV dropout voltage and no more than 40.4 mV undershoot/overshoot. Without significantly increasing the circuit complexity or compromising the tradeoff for active area, it attains high load capacitance to total on-chip capacitance ratio (C_(L(max))/C_T), with respect to the reported counterparts.