The Effect of Manipulating Lead-on-Chip Package Design on Reliability of Semiconductor Devices

摘要

The reliability tests were performed for the qualification of memory devices assembled in small outline J-leaded (SOJ) packages utilizing the lead-on-chip (LOG) die attach technique and it was investigated that the functional failure associated with a passivation break took place during thermal cycling tests. To give a great insight into the passivation cracking phenomena, a mechanism was developed to show that the passivation damage was caused by a polyimide tape used for the bonding of the leadframe on a memory chip. The effect of the bonding tape on the passivation damage was experimentally identified.