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首页> 外文期刊>Journal of Electronic Materials >Low-Roughness Plasma Etching of HgCdTe Masked with Patterned Silicon Dioxide
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Low-Roughness Plasma Etching of HgCdTe Masked with Patterned Silicon Dioxide

机译:图案化二氧化硅掩盖的HgCdTe的低粗糙度等离子体蚀刻

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A novel mask technique utilizing patterned silicon dioxide films has been exploited to perform mesa etching for device delineation and electrical isolation of HgCdTe third-generation infrared focal-plane arrays (IRFPAs). High-density silicon dioxide films were deposited at temperature of 80 deg C, and a procedure for patterning and etching of HgCdTe was developed by standard photolithography and wet chemical etching. Scanning electron microscopy (SEM) showed that the surfaces of inductively coupled plasma (ICP) etched samples were quite clean and smooth. Root-mean-square (RMS) roughness characterized by atomic force microscopy (AFM) was less than 1.5 nm. The etching selectivity between a silicon dioxide film and HgCdTe in the samples masked with patterned silicon dioxide films was greater than 30:1. These results show that the new masking technique is readily available and promising for HgCdTe mesa etching.
机译:已经开发出一种利用图案化的二氧化硅膜的新颖掩模技术来进行台面蚀刻,以进行设备描述和HgCdTe第三代红外焦平面阵列(IRFPA)的电隔离。在80摄氏度的温度下沉积高密度二氧化硅膜,并通过标准光刻和湿法化学蚀刻开发了HgCdTe的图案化和蚀刻程序。扫描电子显微镜(SEM)显示,电感耦合等离子体(ICP)蚀刻样品的表面非常干净且光滑。通过原子力显微镜(AFM)表征的均方根(RMS)粗糙度小于1.5 nm。用图案化的二氧化硅膜掩盖的样品中二氧化硅膜与HgCdTe之间的蚀刻选择性大于30:1。这些结果表明,新的掩膜技术很容易获得,并有望用于HgCdTe台面蚀刻。

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