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Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits

机译:量子点元胞自动机电路中由于随机时钟移位引起的误差建模和评估

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This paper analyzes the effect of random phase shifts in the underlying clock signals on the operation of several basic Quantum-dot Cellular Automata (QCA) building blocks. Such phase shifts can result from manufacturing variations or from uneven path lengths in the clocking network. We perform numerical simulations of basic building blocks using two different simulation engines available in the QCADesigner tool. We assume that the phase shifts are characterized by a Gaussian distribution with a mean value of i(π/2), where i is the clock number and a standard deviation, σ, which is varied in each simulation. Our results indicate that the sensitivity of building blocks to phase shifts depends primarily on the layout while the reliability of all building blocks starts to drop once the standard deviation, σ exceeds 4°. A full adder was simulated to analyze the operation of a circuit featuring a combination of the building blocks considered here. Results are consistent with expectations and demonstrate that the carry output of the full adder is better able to withstand the phase shifts in the clocking network than the Sum output which features a larger combination of the simulated building blocks.
机译:本文分析了基本时钟信号中随机相移对几个基本量子点元胞自动机(QCA)构建块的操作的影响。这种相移可能是由于制造差异或时钟网络中不均匀的路径长度引起的。我们使用QCADesigner工具中提供的两个不同的仿真引擎执行基本构建块的数值仿真。我们假设相移的特征是高斯分布,平均值为i(π/ 2),其中i是时钟数和标准偏差σ,在每次模拟中均会变化。我们的结果表明,构件对相移的敏感性主要取决于布局,而一旦标准偏差σ超过4°,所有构件的可靠性就会开始下降。模拟了一个完整的加法器,以分析以此处考虑的构建块为组合的电路的操作。结果与预期一致,并证明与加法器输出相比,全加法器的进位输出能够更好地承受时钟网络中的相移,而求和输出具有更大的模拟组成部分组合。

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