Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

摘要

Delay line ADCs are becoming increasingly attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay-line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. In this paper, we first present a technique which extends harmonic distortion correction techniques to digital calibration of a delay-line ADC. In our simulation results, digital calibration improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB. In order to reduce the convergence time of the calibration, we inject a periodic 3-bit gray code sequence instead of three pseudorandom numbers for harmonic distortion correction to digitally calibrate an 8-bit delay line ADC. In our simulation results, the SNDR is significantly improved from 25.6 dB to 42.5 dB, with a calibration time of 13.5 milliseconds, which is 64X faster than harmonic distortion correction with the pseudorandom numbers.