Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion Correction

摘要

Delay line ADCs become more and more attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. In this paper, we present a technique which extends harmonic distortion correction techniques to digital calibration of a delay-line ADC. In our simulation results, digital calibration improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB. This strongly supports the scalability of delay line ADCs and their improved performance in further scaled fabrication processes.