Temperature Variation Sensitive 64 Bit Static Random Access Memories Array with Quit Bit Line Technique in a 45 nm CMOS Technology

摘要

High speed and Low power static random access memories (SRAM) has become critical section in present VLSI systems. The on-chip cache sizes are growing with each generation to bridge the increasing deviation in the speeds of the processor and the main memory which is exclusively true for microprocessors. Variation in Temperature with changes threshold voltage, carrier mobility, and saturation velocity and Leakage Current of the CMOS Devices. Temperature variations encourage differences in individual device parameters having unique effects on CMOS Leakage current. This paper explores the design and analysis of 64 bit 7T Static Random Access Memory cells Array with 8-ns access time have been developed on a 45 nm CMOS process technology. We are focused and designed on optimizing leakage current and low power SRAM memory Array using Quiet Bittine technique in which the voltage of bit line stay as low as possible to achieve high-speed with low power using temperature variation on 100 C to 1250 C. Quiet Bit line low power technique avert the unnecessary full-swing charging on the bitline one-side driving scheme for which write operation is used and for read precharged, free-pulling scheme is used to retain all bit lines at low voltages at all times.