Characterization of Layer Stacks in Microelectronic Products: Challenges to Sample Preparation and TEM Analysis

摘要

Thin film and interface characterization are necessary in semiconductor industry to ensure high yields and the required reliability of the products. Particularly, the analysis of layer stacks is a challenging task. Transmission electron microscopy (TEM) essentially contributes to layer stack analysis in microelectronic products. Capabilities and limits of analytical TEM techniques as well as advanced TEM sample preparation techniques are discussed for front-end (MOS transistor) and back-end (interconnect) structures. Typical examples for advanced microprocessor devices are shown.