Low area ASIC implementation of LUT-CLA-QTL architecture for cryptography applications

摘要

The block cipher (BC) algorithm is very fast and easy to standardize and facilitate the hardware (H/W) and software implementations. Thus, in data security BC values are the main constraints in present days. In this paper, a new ultra lightweight BC is implemented which consists of 64-bits BC QTL that supports 128 or 68-bits keys. The conventional Feistel type structure (FTS) is a slow diffusion process, but a new FTS is a fast diffusion process in the QTL structure design. Furthermore, the look-up-table-carry look ahead adder-quantitative trait loci (LUT-CLA-QTL) method is introduced in this paper, which has reduced area, cost and H/W utilization of the system by using LUT-CLA scheme. In this work, an image was read in the MATLAB. That pixel-binary value given to the VLSI then that result given into the Matlab to retrieve the original image. Finally, the decrypted image was equal to the input image. In ASIC implementation, area, power, delay, area power product and area delay product are minimized by using cadence encounter tool with 180 nm and 45 nm library technology. The LUT-CLA-QTL method was achieved less area and power and delay compared to conventional methods.