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Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography

机译:基于超晶体基于量子密码术的超快速模块化倍增器

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As one of the postquantum protocol candidates, the supersingular isogeny key encapsulation (SIKE) protocol delivers promising public and secret key sizes over other candidates. Nevertheless, the considerable computations form the bottleneck and limit its practical applications. The modular multiplication operations occupy a large proportion of the overall computations required by the SIKE protocol. The VLSI implementation of the high-speed modular multiplier remains a big challenge. In this article, we propose three improved modular multiplication algorithms based on an unconventional radix for this protocol, all of which cost about 20% fewer computations than the prior art. Besides, a multiprecision scheme is also introduced for the proposed algorithms to improve the scalability in hardware implementation, resulting in three new algorithms. We then present very efficient high-speed constant-time modular multiplier architectures for the six algorithms. It is shown that these new architectures can be extensively pipelined and highly optimized to obtain high throughput and low latency. The field-programmable gate array (FPGA) implementation results show that all proposed multipliers achieve much higher throughput than previous designs, but the increase in resources is relatively small. In addition, the multipliers without the multiprecision scheme have very low latency, which is very friendly to high-speed applications of the SIKE protocol.
机译:作为后勤协议候选者之一,超出的次源关键封装(SIKE)协议可提供其他候选人的公共和秘密密钥大小。然而,相当大的计算形成了瓶颈并限制了其实际应用。模块化乘法操作占据Sike协议所需的大量总计计算。高速模块倍增器的VLSI实现仍然是一个很大的挑战。在本文中,我们提出了基于本协议的非传统基数的三种改进的模块化乘法算法,所有这些协议都花费了比现有技术的计算约为20%。此外,还引入了多点方案来提出所提出的算法,以提高硬件实现中的可扩展性,从而产生三种新算法。然后,我们为六种算法呈现非常有效的高速恒定时间模块化乘法器架构。结果表明,这些新架构可以广泛流水线,高度优化,以获得高吞吐量和低延迟。现场可编程门阵列(FPGA)实现结果表明,所有提出的乘法器都比以前的设计实现了更高的吞吐量,但资源的增加相对较小。此外,没有多点方案的乘法器具有非常低的延迟,这对SIKE协议的高速应用非常友好。

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