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Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing

机译:低复杂性间隔通过算法和二进制压缩检测的VLSI架构

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摘要

Binary compressed sensing (BCS), in which signals of interest have binary values, finds applications in areas including fault detection and wireless sensor networks. In this article, a low-complexity VLSI architecture for BCS based on interval passing algorithm is proposed. Moreover, the algorithm is modified in order to reduce its complexity without significant loss in performance, and its corresponding VLSI architecture is proposed. Binary low-density parity check (LDPC) matrices based on finite geometry have been used as measurement matrices. The proposed VLSI architectures have been synthesized in both ASIC and field-programmable gate array (FPGA) platforms. The hardware consumption of the proposed designs is independent of sparsity values. Moreover, the proposed architectures offer high frequency of operation and low reconstruction time when compared to the state-of-the-art designs. Specifically, the 65-nm ASIC realization operates at a maximum frequency of 500 and 666.67 MHz and offer a reconstruction time of 6.3 and 4.7 ns, respectively, for a $64imes 256$ deterministic measurement matrix.
机译:二进制压缩检测(BCS),其中感兴趣的信号具有二进制值,在包括故障检测和无线传感器网络的区域中找到应用程序。在本文中,提出了一种基于间隔通过算法的BCS的低复杂性VLSI架构。此外,修改了该算法以减少其复杂性而无需性能显着损失,并且提出了其相应的VLSI架构。基于有限几何体的二进制低密度奇偶校验(LDPC)矩阵已被用作测量矩阵。所提出的VLSI架构已在ASIC和现场可编程门阵列(FPGA)平台中合成。所提出的设计的硬件消耗与稀疏值无关。此外,与最先进的设计相比,所提出的架构提供高频率和低重构时间。具体地,65nm ASIC实现以500和666.67 MHz的最大频率运行,分别为6.3和4.7 ns的重建时间为64次 times 256 $确定性测量矩阵。

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