Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs

摘要

This article presents an approach to providing fault tolerance to permanent effects in the substrate of dynamic, partially reconfigurable field-programmable gate arrays (FPGAs). Our proposal consists of modifying FPGA configuration at runtime to avoid permanently damaged regions of the FPGA. It demands that the circuit design fulfills several requirements regarding the functionality and interfaces of its reconfigurable modules, the structure of the communications, the inclusion of specialized modules to handle and optimize circuit reconfiguration at runtime, and the organization of the reconfigurable partitions. We evaluate two methods to select the new target partition for modules in faulty partitions and design their hardware as intellectual property modules. We evaluate the performance and scalability of this approach using a trapezoidal shaper, a filter used to detect high-energy particles in radiation experiments, and we carry out the experiments with a variable number of modules and reconfigurable partitions using the two selection algorithms. The proposal is compared with nonfault-tolerant and triple modular redundancy approaches, and it remains functional with up to 12x more injected faults than those.