Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters

摘要

Reliability of systems used in space, avionic, and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an analog-to-digital converter (ADC) to convert the collected data to digital form, and a digital unit to process it. Though a considerable amount of research has been performed to increase the reliability of digital blocks, the same cannot be claimed for mixed-signal blocks. The reliability enhancement that we employ begins with fault-sensitivity analysis followed by redesign. The data obtained from the sensitivity analysis is used to grade blocks based on their sensitivity to faults. The highly sensitive blocks can then be replaced by more reliable alternatives. The improvement gained by opting for more robust implementations might be limited due to the number of possible implementations. In these cases, alternative reliability enhancement techniques such as adding redundancy may provide further improvements. The steps involved in the reliability enhancement of ADCs are illustrated in this paper by first proposing a sensitivity analysis methodology for /spl alpha/-particle induced transients and then suggesting redesign techniques to improve the reliability of the ADC. A novel concept of node weights specific to /spl alpha/-particle transients is introduced, which improves the accuracy of the sensitivity analysis. The fault simulations show that, using techniques such as alternative robust implementations, adding redundancy, pattern detection, and transistor sizing, considerable improvements in reliability can be attained.