Automatic synthesis of FPGA channel architecture for routabilityand performance

摘要

This paper considers automatic synthesis of segmented channelnarchitecture of row-based FPGA's so as to achieve maximum routabilitynand performance. The routability of a channel and the performance of thenrouted nets may have conflicting requirements. For a given number ofntracks, very short segments usually enhance routability at the expensenof performance. For such a granular segmented channel architecturenrouting of long nets may require that several short segments be joinedntogether by programming horizontal antifuses. Depending on the antifusentechnology, the programmed antifuses can add considerably to the pathndelays. A channel architecture synthesis algorithm based on simulatednannealing has been developed which enhances channel routability andnperformance. The synthesis algorithm is based on the fact that a strongncorrelation between the spatial distribution of nets and segments in anchannel improves both routability and performance. Excellent resultsnhave been obtained for a set of benchmark examples and industrialndesigns