Certified timing verification and the transition delay of a logiccircuit

摘要

Most research in timing verification has implicitly assumed ansingle vector floating mode computation of delay which is annapproximation of the multivector transition delay. In this paper wenexamine the transition delay of a circuit and demonstrate that thentransition delay of a circuit can differ from the floating delay of ancircuit. We then provide a procedure for directly calculating thentransition delay of a circuit. The most practical benefit of thisnprocedure is the fact that it not only results in a delay calculationnbut outputs a vector sequence that may be timing simulated to certifynstatic timing verification