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Certified timing verification and the transition delay of a logiccircuit

机译:经认证的时序验证和逻辑电路的转换延迟

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Most research in timing verification has implicitly assumed ansingle vector floating mode computation of delay which is annapproximation of the multivector transition delay. In this paper wenexamine the transition delay of a circuit and demonstrate that thentransition delay of a circuit can differ from the floating delay of ancircuit. We then provide a procedure for directly calculating thentransition delay of a circuit. The most practical benefit of thisnprocedure is the fact that it not only results in a delay calculationnbut outputs a vector sequence that may be timing simulated to certifynstatic timing verification
机译:时序验证中的大多数研究都隐含地假设了单个矢量浮点模式的延迟计算,该计算与多矢量转换延迟近似。本文研究了电路的转换延迟,并证明了电路的转换延迟可能不同于电路的浮动延迟。然后,我们提供了直接计算电路转换延迟的过程。此过程的最实际好处是,它不仅会导致延迟计算,而且还会输出可能经过时序仿真以证明静态时序验证的向量序列。

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