Behavioral simulation for analog system design verification

摘要

Synthesis of analog circuits is an emergent field, with effortsnfocused at the cell level. With the growing trend of mixed ASIC designsnthat contain significant portions of analog sections, compatible designnmethodologies in the analog domain are necessary to complement those innthe digital domain. The synthesis process requires an associatednverification process to ensure that the designs meet performancenspecifications at the onset. In this paper we present a behavioralnsimulation methodology for analog system design verification and designnspace exploration. The verification task integrates with analognsystem-level synthesis for an integrated synthesis-verification processnthat avoids expensive post synthesis simulation by invoking externalnsimulators. Thus rapid redesign at the architectural level can benundertaken for design parameter variation and during optimization. Thenverification suite is composed of a repertoire of analysis modes thatninclude time and frequency domain analysis, sensitivity analysis andndistortion analysis. Besides verification of design specifications,nthese analysis modes are also used to generate metrics for comparison ofnvarious architectural choices that could realize a given set ofnspecifications. The implementation is in the form of a behavioralnsimulator, ARCHSIM