Gate-level power and current simulation of CMOS integrated circuits

摘要

In this paper, we present a new gate-level approach to power andncurrent simulation. We propose a symbolic model of complementarynmetal-oxide-semiconductor (CMOS) gates to capture the dependence ofnpower consumption and current flows on input patterns and fan-in/fan-outnconditions. Library elements are characterized and their models are usednduring event-driven logic simulation to provide power information andnconstruct time-domain current waveforms. We provide both global andnlocal pattern-dependent estimates of power consumption and current peaksn(with accuracy of 6 and 10% from SPICE, respectively), while keepingnperformance comparable with traditional gate-level simulation with unitndelay. We use VERILOG-XL as simulation engine to grant compatibilitynwith design tools based on Verilog HDL. A Web-based user interfacenallows our simulator (PPP) to be accessed through the Internet using anstandard web browser