Micropipelined asynchronous discrete cosine transform (DCT/IDCT)processor

摘要

We describe the design and implementation of an asynchronousndiscrete cosine transform/inverse discrete cosine transform (DCT/IDCT)nprocessor core compliant with the CCITT recommendation H.261. First, anmicropipelined implementation with level-sensitive latches is shown.nThis is improved by replacing the level-sensitive latches with dual-edgentriggered flip-flops to save power and using completion-detection addersnin the critical stage of the pipeline to exploit the data-dependentnprocessing delay. Gate-level simulation of extracted layouts indicatesnthat the performance of asynchronous implementations is comparable withnthat of a synchronous implementation based on an identical architecture.nThis is because part of the penalty introduced by handshaking circuitrynin an asynchronous pipeline can be recovered by exploitingndata-dependent processing delays with completion-detection circuitry. Innpipelines with significant arithmetic processing such as the DCT/IDCTnprocessor, this is easily accomplished. Our results are encouragingnbecause asynchronous designs do not employ global clocking. In the nearnfuture when clock generation, clock distribution, and the power consumednin the clock circuitry become limiting factors in the design of largensynchronous application specific integrated circuits (ASICs),nasynchronous implementation methodology could be pursued as a realnalternative