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Efficient VLSI for Lempel-Ziv compression in wireless datacommunication networks

机译:无线数据通信网络中用于Lempel-Ziv压缩的高效VLSI

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We present a parallel algorithm, architecture, and implementationnfor efficient Lempel-Ziv (LZ)-based data compression. The parallelnalgorithm exhibits a scalable, parameterized, and regular structure andnis well suited for VLSI array implementation. Based on our parallelnalgorithm and systematic design methodologies, two semisystolic arraynarchitectures have been developed which are low power and areanefficient. The first architecture trades off the compression speed fornthe area and has a low run-time overhead for multichannel compression.nThe second architecture achieves a high compression rate (one datansymbol per clock) at the expense of the area due to a large clock loadnand global wiring. Compared to a recent state-of-the-art parallelnarchitecture, our first array structure requires significantly less chipnarea (≃330 k versus ≃36 k transistors) and more than an ordernof magnitude less power (≈1.0 W versus ≈70 mW) while stillnproviding the compression speed required for most data communicationnapplications. Hence, data compression can be adopted in portable datancommunication as well as wireless local area networks. The secondnarchitecture has at least three times less area and power whilenproviding the same constant compression rate. To demonstrate thencorrectness of our design, a prototype module for the first architecturenhas been implemented using 1.2 Μ complementarynmetal-oxide-semiconductor (CMOS) technology. The compression modulencontains 32 simple and identical processors, has an average compressionnrate of 12.5 million bytes/s, and consumes 18.34 mW without thendictionary (≈70 mW with a 4.1k SRAM for the dictionary) whilenoperating at a 100 MHz clock rate (simulated)
机译:我们提出了一种基于高效Lempel-Ziv(LZ)的数据压缩的并行算法,体系结构和实现。并行算法具有可扩展的,参数化的和规则的结构,非常适合VLSI阵列实现。基于我们的并行算法和系统设计方法,已开发出两种半收缩阵列架构,它们功耗低且效率高。第一种架构在此区域的压缩速度之间进行权衡,并且多通道压缩的运行时开销较低。第二种架构由于时钟负荷大和全局布线而以面积为代价实现了高压缩率(每个时钟一个数据符号)。 。与最近的最新并行架构相比,我们的第一个阵列结构所需的芯片面积大大减少(≃ 330 k vs.sime; 36 k晶体管),功耗也降低了一个数量级(≈ 1.0 W vs≈ 70)。 mW),同时仍为大多数数据通信应用程序提供所需的压缩速度。因此,可以在便携式数据通信以及无线局域网中采用数据压缩。第二架构具有至少三倍的面积和功率,同时提供了相同的恒定压缩率。为了证明我们设计的正确性,已经使用1.2 M互补金属氧化物半导体(CMOS)技术实现了第一个架构的原型模块。压缩模块n包含32个简单且相同的处理器,平均压缩速率为1,250万字节/秒,在不使用字典的情况下功耗为18.34 mW(对于字典为4.1k SRAM,功耗为70 mW),同时以100 MHz时钟速率运行(模拟)

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