Concurrent fault simulation on message passing multicomputers

摘要

Even though hardware accelerators are common in very large scalenintegration (VLSI) computer-aided design (CAD), fault simulation is annotable exception because of limited availability of memory, the neednfor dynamic memory management and the complexity of the algorithmsnthemselves. Although simplified fault simulation algorithms that assumena zero delay circuit model can be accelerated, their applicability isnlimited. Most application specific integrated circuits (ASIC's) designednin industry today have on-chip memory blocks of different dimensions andncharacteristics, enhancing the complexity of a fault simulator. In thisnpaper, we present a multiple delay algorithm for concurrent faultnsimulation of logic gates and functional memory blocks. This algorithmnhas been implemented on the microprogrammable accelerator for rapidnsimulation (MARS) hardware accelerator system with a 22 MHz clock and ancapacity to simulate circuits with millions of devices. Speedup factorsnof 20 to 30 are easily achieved when compared to software simulatorsnrunning on comparable hardware platforms and using identical circuitnmodels