Improving functional density using run-time circuit reconfiguration[FPGAs]

摘要

The ability to provide flexibility and allow fine-grain circuitnspecialization make field programmable gate arrays (FPGA's) idealncandidates for computing elements within application-specificnarchitectures. The benefits of gate-level specialization andnreconfigurability can be extended by reconfiguring circuit resources atnrun-time. This technique, termed run-time reconfiguration (RTR), allowsnthe exploitation of dynamic conditions or temporal locality withinnapplication-specific problems. For several applications, this techniquenhas been shown to reduce the hardware resources required forncomputation. The use of this technique on conventional FPGA's, however,nrequires additional time for circuit reconfiguration. A functionalndensity metric is introduced that balances the advantages of RTR againstnits associated reconfiguration costs. This metric is used to justifynrun-time reconfiguration against other more conventional approaches.nSeveral run-time reconfigured applications are presented and analyzednusing this approach