Interfacing synchronous and asynchronous modules within ahigh-speed pipeline

摘要

This paper describes a new technique for integrating asynchronousnmodules within a high-speed synchronous pipeline. Our design eliminatesnpotential metastability problems by using a clock generated by anstoppable ring oscillator, which is capable of driving the large clocknload found in present day microprocessors. Using the ATACS design tool,nwe designed highly optimized transistor-level circuits to control thenring oscillator and generate the clock and handshake signals withnminimal overhead. Our interface architecture requires no redesign of thensynchronous circuitry. Incorporating asynchronous modules in anhigh-speed pipeline improves performance by exploiting data-dependentndelay variations. Since the speed of the synchronous circuitry tracksnthe speed of the ring oscillator under different processes,ntemperatures, and voltages, the entire chip operates at the speedndictated by the current operating conditions, rather than being governednby the worst case conditions. These two factors together can lead to ansignificant improvement in average-case performance. The interfacendesign is simulated using the 0.6-Μm HP CMOS14B process in HSPICE