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Design of self-checking fully differential circuits and boards

机译:自检全差动电路板设计

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A design methodology for on-line testing analog linear fullyndifferential (FD) circuits is presented in this work. The test strategynis based on concurrently monitoring via an analog checker the commonnmode (Chi) at the inputs of all amplifiers, The totally self-checkingn(TSC) goal is achieved for linear FD implementations provided that thenchecker CM threshold is small enough with respect to the specifiednmargins of erroneous behavior in the circuit outputs. The designnmethodology is illustrated for a switched-capacitor biquadratic filternand the self-checking properties evaluated for a hard/soft-fault model.nA large checker threshold of 100 mV of CM is chosen since the filternimplementation does not minimize nonidealities (e.g., amplifier offsetsnor clock feedthrough) which result in significant CM components. Thencircuit outputs are accepted to deviate within a 10% band. With thenimplemented checker, the TSC goal is not achieved for some faults innnarrow regions of the frequency band. For the worst case, a hard faultnwhich results in a 31% deviation is undetected in only a narrow band ofnapproximately 310 Hz. The circuit can be made TSC with a checkernthreshold of 40 mV and an accepted output deviation of 15%. This is,nhowever, more demanding on the checker (which currently takes less thann3% of the total area and about 7.6% of the total power) and requires annimproved filter implementation to reduce CM components. Our solutionnconsists of relaxing a bit the TSC property of the functional block andnapplying a periodical off-line test to make the checker strongly codendisjoint (SCD). This is easy to implement since an off-line test is alsonrequired for the checker. The checker outputs a double-rail errornindication which ensures compatibility with digital checkers and makesnthe design of self-checking mixed signal circuits straightforward. Thencircuit-level mixed-signal approach is extended to the board level bynmeans of the IEEE Std. 1149.1 digital test bus
机译:在这项工作中提出了一种用于在线测试模拟线性全微分(FD)电路的设计方法。该测试策略基于通过模拟校验器同时监视所有放大器输入端的共模(Chi),实现线性FD实现的完全自校验n(TSC)目标,前提是校验器CM阈值相对于在电路输出中指定了错误行为的nmargins。举例说明了开关电容双二次滤波器的设计方法,并针对硬/软故障模型评估了自检特性。n选择了100 mV CM的大检查阈值,因为滤波器的实现并未使非理想性最小化(例如,放大器失调或时钟)馈通),从而导致大量CM组件。然后电路输出将在10%的范围内发生偏差。使用当时实现的检查器,对于频带的某些故障区域而言,TSC目标无法实现。在最坏的情况下,仅在大约310 Hz的窄带中未检测到导致31%偏差的硬故障。可以将电路制成TSC,方格阈值为40 mV,可接受的输出偏差为15%。但是,这对检查器提出了更高的要求(当前检查器仅占总面积的不到n3%,而仅占总功率的7.6%),并且需要改进滤波器的实现以减少CM组件。我们的解决方案包括放宽功能块的TSC属性,并应用定期的离线测试以使检查器具有强编码不相交(SCD)。这很容易实现,因为检查器也不需要离线测试。该校验器输出双轨错误指示,以确保与数字校验器的兼容性,并使自校验混合信号电路的设计变得简单。然后,电路级混合信号方法通过IEEE Std的标准扩展到板级。 1149.1数字测试总线

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