Carry chains are an important consideration for most computations, including FPGA's. Current FPGA's dedicate a portion of their logic to support these demands via a simple ripple carry scheme. In this paper, we demonstrate how more advanced carry constructs can he embedded into PPGA's, providing significantly higher performance carry computations. We redesign the standard ripple carry chain to reduce the number of logic levels in each cell. We also develop entirely new carry structures based on high-performance adders such as carry select, carry lookahead, and Brent-Kung. Overall, these optimizations achieve a speedup in carry performance of 3.8 times over current architectures.
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