基于FPGA进位链TDC延时模型的建立与性能测试

摘要

Time- of- flight (TOF) information would improve the performance of PET (positron emission tomography). TDC design is a key technique. It proposed Carry Chain TDG Delay model. Through changing the significant delay parameter of model, paper compared the difference of TDC performance, and finally realized Time- to- Digital Convertor (TDC) based on Carry Chain Method using FPGA EP2C20Q240C8N with 69 ps LSB, max error below 2 LSB. Such result could meet the TOF demand. It also proposed a Coaxial Cable Measuring method for TDC testing , without High - precision test equipment.%引入飞行时间信息,可以提高正电子断层显像仪(Positron Ernission Tomography,PET)系统的性能.电子学时间数字转换(TDC,Time-to-Digital Convertor)设计是其中一项关键技术.论文针对进位链(Carty Chain)TDC设计,建立了TDC的延时模型,推导了进位链TDC的延时公式.基于模型,通过调整关键信号的参数,比较了调整前后的TDC性能,在EP2C20Q240C8N芯片上实现和提升了进位链TDC的性能,最小测量间隔为69 ps,测量误差小于2 LSB,能够满足TOF测量时间精度的要求,并验证了模型公式的正确性.对TDC的测试方法选用高精度同轴电缆进行间接测量,解决了在缺乏ps级高精度测试设备情况下的时间精度测试问题.