A novel and efficient routing architecture for multi-FPGA systems

摘要

Multi-FPGA systems (MFSs) are used as custom computing machines,nlogic emulators and rapid prototyping vehicles. A key aspect of thesensystems is their programmable routing architecture which is the mannernin which wires, FPGAs and field-programmable interconnect devicesn(FPIDs) are connected. Several routing architectures for MFSs have beennproposed, and previous research has shown that the partial crossbar isnone of the best existing architectures. In this paper, we propose a newnrouting architecture, called the hybrid complete-graph andnpartial-crossbar (HCGP) which has superior speed and cost compared to anpartial crossbar. The new architecture uses both hard-wired andnprogrammable connections between the FPGAs. We compare the performancenand cost of the HCGP and partial crossbar architectures experimentally,nby mapping a set of 15 large benchmark circuits into each architecture.nA customized set of partitioning and interchip routing tools werendeveloped, with particular attention paid to architecture-appropriateninterchip routing algorithms. We show that the cost of the partialncrossbar (as measured by the number of pins on all FPGAs and FPIDsnrequired to fit a design), is on average 20% more than the new HCGPnarchitecture and as much as 25% more. Furthermore, the critical pathndelay for designs implemented on the partial crossbar were on averagen20% more than the HCGP architecture and up to 43% more. Using ournexperimental approach, we also explore a key architecture parameternassociated with the HCGP architecture-the proportion of hard-wirednconnections versus programmable connections-to determine its best value