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Efficient inductance extraction using circuit-aware techniques

机译:使用电路感知技术有效提取电感

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Proposes two practical approaches for on-chip inductance extraction to obtain a highly sparsified and accurate inverse inductance matrix K. Both approaches differ from previous methods in that they use circuit characteristics to obtain a sparse, stable and symmetric K, using the concept of resistance-dominant and inductance-dominant lines. Specifically, they begin by finding inductance-dominant lines and forming initial clusters, followed by heuristically enlarging and/or combining these clusters, with the goal of including only the important inductance terms in the sparsified K matrix. Algorithm 1 permits the influence of the magnetic field of aggressor lines to reach the edge of the chip, while Algorithm 2 works under the simplified assumptions that the supply lines have zero /spl Sigma//sub j/L/sub ij/(dI/sub j//dt) drops (but have nonzero parasitic Rs and Cs) and that currents cannot return through supply lines beyond a user-defined distance. For reasonable designs, Algorithm 1 delivers a sparsification of 97% for delay and oscillation magnitude errors of 10% and 15%, respectively, as compared to Algorithm 2 where the sparsification can reach 99% for the same delay error.
机译:提出了两种实用的片上电感提取方法,以获得高度稀疏且准确的逆电感矩阵K。这两种方法与以前的方法不同之处在于,它们使用电路特性来获得稀疏,稳定和对称的K,并采用了电阻-主导线和电感主导线。具体而言,它们从找到电感占优势的线并形成初始簇开始,然后试探性地扩大和/或组合这些簇,目的是仅将重要的电感项包括在稀疏的K矩阵中。算法1允许干扰线的磁场影响到达芯片边缘,而算法2在简化假设下工作,即电源线为零/ spl Sigma // sub j / L / sub ij /(dI / sub j // dt)下降(但寄生Rs和Cs不为零),并且电流无法通过用户定义距离以外的电源线返回。对于合理的设计,与算法2相比,算法1对10%和15%的延迟和振荡幅度误差提供了97%的稀疏度,而对于相同的延迟误差,算法2的稀疏度可以达到99%。

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