False path exclusion in delay analysis of RTL structures

摘要

In this paper, we present an accurate delay-estimation algorithmnat the register-transfer level. We study three important sources ofnfalse paths in register-transfer-level (RTL) structures, i.e., 1)nresource binding; 2) interdependent conditions; and 3)ndatapath-controller path mismatching. The existence and creation of suchnpaths and their effects in delay analysis are discussed. We show that inna RTL datapath structure the accuracy of the delay estimators isnaffected by the existence of false paths. Specifically, the accuracyndrops significantly for structures synthesized from condition-dominatednbehaviors. We propose a mechanism to efficiently avoid false paths inndelay analysis. This is achieved by introducing the propagation delayngraph (PDG), whose traversal for delay analysis is equivalent to thentraversal of sensitizable paths in the datapath. Comparison with thentiming verifier in commercial computer-aided design (CAD) tools, shownthat estimated delays are within 14% accuracy of those reported by CADntools