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Voltage-pulse driven harmonic resonant rail drivers for low-power applications

机译:电压脉冲驱动的谐波谐振导轨驱动器,适用于低功率应用

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We describe a new design technique for efficient harmonic resonant rail drivers. The proposed circuit implementation is coupled to a standard pulse source and uses only discrete passive components and no external dc power supply. It can thus be externally tuned to minimize the consumed power in the target IC. A new design technique based on current-fed voltage pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed circuit topology can be used to generate any desired periodic 50% duty-cycle waveform by superimposing multiple harmonics of the desired waveform, however, this paper focuses on the generation of trapezoidal-wave clock signals. We have tested the driver with a capacitive load between 38.3 and 97.8 pF with clock frequency ranging between 0.8 and 15 MHz. The overall power dissipation for our second-order harmonic rail driver is 19% of fC/sub L/V/sup 2/ at 15 MHz and 97.8 pF load.
机译:我们描述了一种用于高效谐波谐振轨道驱动器的新设计技术。所提出的电路实现方式耦合到标准脉冲源,并且仅使用分立的无源元件,而没有外部直流电源。因此,可以对其进行外部调整以最小化目标IC的功耗。提出了一种基于电流反馈电压脉冲形成网络理论的新设计技术,以求出目标频率和给定负载电容下每个离散分量的值。所提出的电路拓扑可用于通过叠加所需波形的多个谐波来生成任何所需的周期性50%占空比波形,但是,本文着重于梯形波时钟信号的生成。我们已经测试了驱动器在38.3至97.8 pF之间的容性负载,时钟频率在0.8至15 MHz之间。在15 MHz和97.8 pF负载下,我们的二阶谐波轨驱动器的总功耗为fC / sub L / V / sup 2 /的19%。

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