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Techniques for accurate performance evaluation in architecture exploration

机译:在架构探索中进行准确性能评估的技术

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We present a system that automatically generates a cycle-accurate and bit-true instruction level simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS can be used to obtain a cycle count for a given program running on the target architecture, while the cycle length, die size, and power consumption can be obtained from the hardware implementation model. These figures allow us to accurately and rapidly evaluate target architectures within an architecture exploration methodology for system-level synthesis. In an architecture exploration scheme, both the ILS and the hardware model must be generated automatically, else a substantial programming and hardware design effort has to be expended in each design iteration. Our system uses the Instruction Set Description language to support the automatic generation of the ILS and the hardware synthesis model, as well as other related tools.
机译:我们提出了一种系统,该系统会自动生成周期精确且位真的指令级模拟器(ILS)和给出目标处理器描述的硬件实现模型。 ILS可用于获取在目标体系结构上运行的给定程序的周期数,而周期长度,管芯尺寸和功耗可从硬件实现模型中获得。这些数字使我们能够在用于系统级综合的体系结构探索方法中准确,快速地评估目标体系结构。在架构探索方案中,必须自动生成ILS和硬件模型,否则在每次设计迭代中都必须花费大量的编程和硬件设计工作。我们的系统使用指令集描述语言来支持ILS和硬件综合模型以及其他相关工具的自动生成。

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