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Address-free memory access based on program syntax correlation of loads and stores

机译:基于程序语法加载和存储的无地址内存访问

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An increasing cache latency in next-generation processors incurs profound performance impacts in spite of advanced out-of-order execution techniques. One way to circumvent this cache latency problem is to predict load values at the onset of pipeline execution by exploiting either the load value locality or the address correlation of stores and loads. In this paper, we describe a new load value speculation mechanism based on the program syntax correlation of stores and loads. We establish a symbolic cache (SC) , which is accessed in early pipeline stages to achieve a zero-cycle load. Instead of using memory addresses, the SC is accessed by the encoding bits of base register ID plus the displacement directly from the instruction code. Performance evaluations using SPEC95 and SPEC2000 integer programs on SimpleScalar simulation tools show that the SC achieves higher prediction accuracy in comparison with other load value speculation methods, especially when hardware resources are limited.
机译:尽管采用了先进的无序执行技术,但下一代处理器中不断增加的缓存等待时间仍会对性能产生重大影响。规避此缓存延迟问题的一种方法是,通过利用负载值局部性或存储和负载的地址相关性,在管道执行开始时预测负载值。在本文中,我们基于存储和负载的程序语法相关性描述了一种新的负载值推测机制。我们建立了符号缓存(SC),可以在早期管道阶段对其进行访问以实现零周期负载。代替使用存储器地址,通过基址寄存器ID的编码位加上直接从指令代码中进行的位移来访问SC。在SimpleScalar仿真工具上使用SPEC95和SPEC2000整数程序进行的性能评估表明,与其他负载值推测方法相比,SC可以实现更高的预测精度,尤其是在硬件资源有限的情况下。

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