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A hardware Gaussian noise generator using the Wallace method

机译:使用Wallace方法的硬件高斯噪声发生器

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We describe a hardware Gaussian noise generator based on the Wallace method used for a hardware simulation system. Our noise generator accurately models a true Gaussian probability density function even at high /spl sigma/ values. We evaluate its properties using: 1) several different statistical tests, including the chi-square test and the Anderson-Darling test and 2) an application for decoding of low-density parity-check (LDPC) codes. Our design is implemented on a Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) at 155 MHz; it takes up 3% of the device and produces 155 million samples per second, which is three times faster than a 2.6-GHz Pentium-IV PC. Another implementation on a Xilinx Spartan-III XC3S200E-5 FPGA at 106 MHz is two times faster than the software version. Further improvement in performance can be obtained by concurrent execution: 20 parallel instances of the noise generator on an XC2V4000-6 FPGA at 115 MHz can run 51 times faster than software on a 2.6-GHz Pentium-IV PC.
机译:我们描述了一种基于用于硬件仿真系统的Wallace方法的硬件高斯噪声发生器。即使在高/ spl sigma /值下,我们的噪声发生器也可以准确地建模真实的高斯概率密度函数。我们使用以下方法评估其属性:1)几种不同的统计检验,包括卡方检验和安德森-达林检验,以及2)用于解码低密度奇偶校验(LDPC)码的应用程序。我们的设计在155 MHz的Xilinx Virtex-II XC2V4000-6现场可编程门阵列(FPGA)上实现;它占用了3%的设备,每秒可产生1.55亿个样本,这是2.6 GHz Pentium-IV PC的三倍。在Xilinx Spartan-III XC3S200E-5 FPGA上以106 MHz的另一种实现比软件版本快两倍。通过并发执行,可以进一步提高性能:XC2V4000-6 FPGA上115 MHz的20个并行噪声发生器实例的运行速度比2.6 GHz Pentium-IV PC上的软件快51倍。

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