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Coding for system-on-chip networks: a unified framework

机译:片上系统网络的编码:统一框架

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Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-/spl mu/m CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17/spl times/ speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7/spl times/ speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.
机译:深亚微米(DSM)片上系统设计中的全局总线消耗大量功率,具有较大的传播延迟,并且容易因DSM噪声而产生错误。存在可以单独解决这些问题的编码方案。在本文中,我们提出了一种从DSM总线的通信理论观点出发的编码框架,以共同解决功耗,延迟和可靠性。在此框架中,数据首先通过非线性源编码器传递,该源编码器减少了自身和耦合跃迁的活动,并对总线上的峰值耦合跃迁施加了约束。接下来,线性错误控制编码器添加冗余以实现错误检测和纠正。该框架用于有效地组合现有代码,并获得新颖的代码,这些代码跨越了总线延迟,编解码器延迟,功率,面积和可靠性之间的广泛折衷。使用0.13- / spl mu / m CMOS技术的仿真结果,我们表明编码是中继器插入的一种更好的替代方法,可以减少延迟,因为它可以同时降低功耗。对于10毫米4位总线,我们证明,与使用汉明代码的总线相比,采用建议代码的总线可实现高达2.17 / spl次/加速,并节省33%的能源。对于10毫米32位总线,我们证明,通过采用低摆幅信号传输,在未编码总线上可实现1.7 / spl次/加速,并减少27%的能量,而不会损失任何可靠性。

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