首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips
【24h】

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

机译:SAMBA-Bus:用于片上系统的高性能总线体系结构

获取原文
获取原文并翻译 | 示例

摘要

A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus architecture, multiple compatible bus transactions can be performed simultaneously with only a single bus access grant from the bus arbiter. Experimental results show that, compared with a traditional bus architecture, the SAMBA-bus architecture can have up to 3.5 times improvement in the effective bandwidth, and up to 15 times reduction in the average communication latency. In addition, the performance of SAMBA-bus architecture is affected only slightly by arbitration latency, because bus transactions can be performed without waiting for the bus access grant from the arbiter. This feature is desirable in SoC designs with large numbers of modules and long communication delay between modules and the bus arbiter.
机译:本文提出了一种高性能的通信架构SAMBA-bus。在SAMBA总线体系结构中,可以同时执行多个兼容的总线事务,而仅从总线仲裁器获得单个总线访问权限即可。实验结果表明,与传统的总线体系结构相比,SAMBA总线体系结构的有效带宽提高了3.5倍,平均通信延迟降低了15倍。另外,SAMMBA总线体系结构的性能仅受仲裁延迟的影响很小,因为可以执行总线事务而无需等待仲裁者的总线访问权限。此功能在具有大量模块且模块与总线仲裁器之间的通信延迟较长的SoC设计中是理想的。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号