692-nW Advanced Encryption Standard (AES) on a 0.13- m CMOS

摘要

This paper presents a very low power/area design for the advanced encryption standard (AES) based on an 8-bit data path. The average measured core power on a 0.13-$mu$m CMOS using a 100-kHz clock and a core voltage of 0.75 V is 692 nW. The core area is 21 000 $mu{hbox {m}}^{2}$ and the latency is 356 cycles. This design further challenges the low-resource end of the design space and is the first reported submicrowatt design for the AES; it has significant power–latency–area performance improvements over the previous state-of-the-art application-specific IC (ASIC) implementations.