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Compressive Acquisition CMOS Image Sensor: From the Algorithm to Hardware Implementation

机译:压缩采集CMOS图像传感器:从算法到硬件实现

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In this paper, a new design paradigm referred to as compressive acquisition CMOS image sensors is introduced. The idea consists of compressing the data within each pixel prior to storage, and hence, reducing the size of the memory required for digital pixel sensor. The proposed compression algorithm uses a block-based differential coding scheme in which differential values are captured and quantized online. A time-domain encoding scheme is used in our CMOS image sensor in which the brightest pixel within each block fires first and is selected as the reference pixel. The differential values between subsequent pixels and the reference within each block are calculated and quantized, using a reduced number of bits as their dynamic range is compressed. The proposed scheme enables reduced error accumulation as full precision is used at the start of each block, while also enabling reduced memory requirement, and hence, enabling significant silicon area saving. A mathematical model is derived to analyze the performance of the algorithm. Experimental results on a field-programmable gate-array (FPGA) platform illustrate that the proposed algorithm enables more than 50% memory saving at a peak signal-to-noise ratio level of 30 dB with 1.5 bit per pixel.
机译:在本文中,介绍了一种称为压缩采集CMOS图像传感器的新设计范例。该思想包括在存储之前压缩每个像素内的数据,并因此减小数字像素传感器所需的存储器大小。所提出的压缩算法使用基于块的差分编码方案,其中差分值被在线捕获和量化。在我们的CMOS图像传感器中使用了一种时域编码方案,其中每个块中最亮的像素首先触发,然后被选作参考像素。使用减少的位数(因为压缩了它们的动态范围)来计算和量化每个块中后续像素和参考之间的差分值。由于在每个块的开头都使用了全精度,因此提出的方案可以减少错误累积,同时还可以减少存储需求,从而可以节省大量的硅面积。导出数学模型以分析算法的性能。在现场可编程门阵列(FPGA)平台上的实验结果表明,所提出的算法在30 dB的峰值信噪比水平(每像素1.5位)下实现了50%以上的内存节省。

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