A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-$mu{rm m}$ CMOS

摘要

This paper presents a between-pair skew (BPS) compensator for parallel data communications. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a wide-bandwidth voltage controlled data delay line. A 5-Gb/s sub-bit BPS compensator in 0.13-$mu{rm m}$ CMOS occupies approximately 0.038-${rm mm}^{2}$ active die area and dissipates 22.5 mW.