Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS

摘要

This paper describes the characteristics of a half-rate clock-embedded source-synchronous signaling scheme to identify its constraints and to optimize the transceiver topology in the presence of a band-limited channel. The proposed signaling combines the half-rate clock to the common mode of the differential data with its mixing phase off by 0.5 UI. Two transceivers with resistive-load and inductive-load receivers are implemented in 130-nm CMOS technology to verify their feasibility for use as serial links. The prototype transceivers achieve a wide operating frequency range 2.25–6 and 5.6–8 Gb/s, respectively, satisfying bit error rate of ${<}{10}^{-12}$ measured at Tx–Rx linked configuration by 5-in-long FR4 trace with $2^{31}-1$ PRBS. The power efficiencies of transceivers at maximum data rates are 6.4 and 4.6 mW/Gb/s, respectively.