A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF src='/images/tex/29716.gif' alt='(2^{m})'>

摘要

This paper presents a novel low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF. For an input circuit, the proposed scheme can correct multiple error combinations out of all the possible errors, which is superior to many existing approaches. From the mathematical and practical evaluations, the best case error correction is bit errors. Tests on 80-bit parallel and, for the first time, on 163-bit Federal Information Processing Standard/National Institute of Standards and Technology (FIPS/NIST) standard word-level Galois field (GF) multipliers, suggest that it requires only 106% and 170% area overheads, respectively, which is lower than the existing approaches, while error injection-based behavioral analysis demonstrates its wider error correction capability.