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A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology

机译:基于晶体In-Ga-Zn-O技术的具有改进的开关特性且无过驱动的升压通过门用于可编程路由开关

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A boosting pass gate (BPG) suitable for a programmable routing switch including a c-axis aligned crystal In-Ga-Zn-O (CAAC-IGZO) field effect transistor (FET) is proposed. The CAAC-IGZO is one of crystalline oxide semiconductors (OS). The proposed BPG (OS-based BPG, OS BPG) has a combination of a pass gate (PG) and a configuration memory (CM) cell utilizing a CAAC-IGZO FET with extremely low OFF-state current and a storage capacitor. This OS BPG achieves a routing switch with fewer transistors than a conventional routing switch having a combination of a PG and an static RAM (SRAM) cell. Owing to the boosting effect, the switching characteristics, at not only positive transition but also negative transition of input signals, of the OS BPG are improved without using overdriving. In circuits fabricated with a hybrid process of a CMOSFET and a CAAC-IGZO FET with gate lengths of 0.5 and 1.0 μm, the net delays of the OS BPG, 75 and 58 ns, at driving voltages of 2.0 and 2.5 V have been found to be less than those of the conventional routing switch (SRAM-based PG, SRAM PG) by about 79% and 62%, respectively. It has also been confirmed that a field-programmable gate array (FPGA) chip utilizing the OS BPG as a routing switch reduces the layout areas of routing switches and the whole chip by 61% and 22%, respectively, and increases the maximum operating frequencies at driving voltage of 2.0 and 2.5 V by about 2.8 times and 1.6 times of those of the FPGA chip utilizing the SRAM PG as a routing switch.
机译:提出了一种适用于包括c轴对准晶体In-Ga-Zn-O(CAAC-IGZO)场效应晶体管(FET)的可编程路由开关的升压通过门(BPG)。 CAAC-IGZO是晶体氧化物半导体(OS)之一。提出的BPG(基于OS的BPG,OS BPG)具有通过门(PG)和配置存储器(CM)单元的组合,该单元使用具有极低截止态电流的CAAC-IGZO FET和存储电容器。与具有PG和静态RAM(SRAM)单元的组合的常规路由开关相比,此OS BPG用更少的晶体管实现了路由开关。由于升压作用,OS BPG不仅在输入信号的正跃迁而且在输入信号的负跃迁处的开关特性得到改善,而无需使用过驱动。在采用CMOSFET和CAAC-IGZO FET的混合工艺制造的电路中,栅极长度分别为0.5和1.0μm,在驱动电压为2.0和2.5 V的情况下,OS BPG的净延迟分别为75和58 ns。分别比传统的路由交换机(基于SRAM的PG,SRAM PG)小大约79%和62%。还已经确认,利用OS BPG作为路由交换机的现场可编程门阵列(FPGA)芯片分别将路由交换机和整个芯片的布局面积减少了61%和22%,并提高了最大工作频率驱动电压为2.0和2.5 V,分别是使用SRAM PG作为路由开关的FPGA芯片的2.8倍和1.6倍。

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