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An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

机译:支持动态控制电源门控的FPGA架构和CAD流程

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Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time; the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application.
机译:泄漏功率是使用90纳米及更小的技术节点构建的现场可编程门阵列(FPGA)的总功耗的重要组成部分。功率门控被证明在减少泄漏功率方面是有效的。先前的技术着重于在配置时关闭未使用的FPGA资源。这种方法的好处取决于资源的利用。在本文中,我们介绍了一种可实现动态控制电源门控的FPGA架构,其中FPGA资源可在运行时选择性关闭。对于具有较长空闲时间的模块的应用程序,这可能会节省大量的总体能源。我们还提出了一个CAD流程,可用于将应用程序映射到所建议的体系结构。我们通过改变不同的FPGA架构参数和功率门控粒度来研究面积和功率的权衡。建议的CAD流程用于将一组具有多个电源门控模块的基准电路映射到建议的体系结构。这些电路可节省多达83%的功率。最后,我们研究了用于内窥镜检查的机器人的控制系统。在本应用中,将建议的架构与时钟门控结合使用可节省多达19%的能源。

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