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A DAC With an Impedance Attenuator and Distortion Analysis Using Volterra Series

机译:使用Volterra系列的具有阻抗衰减器和失真分析的DAC

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An impedance attenuator is implemented to reduce digital-to-analog converter (DAC) distortion, and two techniques to further reduce the distortion are discussed: the first is to use cross-coupled capacitors to cancel nonlinear currents; the second is to optimize the common-mode bandwidth of the differential amplifier for cancellation of distortion. To support these techniques, DAC distortion has been analyzed with the Volterra series, and the analysis is compared with simulation results and measurement data. The analysis uncovers a previously unknown nonlinear cancellation mechanism for the DAC and confirms the proposed techniques. Each technique can contribute 3-6 dB of improvement, and about a 6-dB improvement when combined. The 0.708-mm DAC is fabricated in a 28-nm metal-gate digital CMOS process with the proposed impedance attenuator, and it achieves -89 dBc of average HD3 at a 5-MHz input frequency and sampling rate of 230.4 MHz.
机译:实现了阻抗衰减器以减少数模转换器(DAC)的失真,并讨论了两种进一步减小失真的技术:第一种是使用交叉耦合电容器来消除非线性电流;第二是优化差动放大器的共模带宽,以消除失真。为了支持这些技术,已使用Volterra系列分析了DAC失真,并将分析结果与仿真结果和测量数据进行了比较。分析发现了DAC以前未知的非线性消除机制,并证实了所提出的技术。每种技术都可以贡献3-6 dB的改善,结合起来可以改善6-dB。 0.708毫米DAC采用建议的阻抗衰减器在28纳米金属栅数字CMOS工艺中制造,在5 MHz输入频率和230.4 MHz采样率下,其平均HD3达到-89 dBc。

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