Improving DRAM Performance in 3-D ICs via Temperature Aware Refresh

摘要

The 3-D integration allows IC designs to stack DRAM directly on the top of execution units, which greatly reduces DRAM access latency and improves memory bandwidth. Unfortunately, the heat generated by the processor unit cannot be effectively dissipated. As a result, DRAM operating temperature is undesirably increased. Due to the fact that 3-D-stacked DRAM operates under a severe thermal condition manifested as escalated hot spots and large temperature gradients, conventional refresh schemes based on the peak temperature lead to high refresh rates, which introduce large performance degradation in 3-D-stacked DRAM. To address this problem, we propose the temperature aware refresh technique for 3-D-stacked DRAM. The goal is to mitigate this performance degradation by adjusting the refresh rates of DRAM banks based on their actual thermal conditions at runtime. As a result, only banks that work in the peak temperature will refresh frequently, while the rest of the banks can be refreshed at a reduced rate. This enables more read and write accesses, which improves the overall memory performance.